DS1388Z-3+T&R【PDF 6/19 页】IC RTC I2C W/CHARGER 8-SOIC

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I2C RTC/Supervisor with Trickle Charger

and 512 Bytes EEPROM

Maxim Integrated

DS1388

EEPROM

The DS1388 provides 512 bytes of EEPROM organized

into two blocks of 256 bytes. Each 256-byte block is

divided into 32 pages consisting of 8 bytes per page.

The EEPROM can be written one page at a time. Page

write operations are limited to writing bytes within a sin-

gle physical page, regardless of the number of bytes

actually being written. Physical page boundaries start at

addresses that are integer multiples of the page size (8

bytes) and end at addresses that are integer multiples

of [page size -1]. For example, page 0 contains word

addresses 00h to 07h. Similarly, page 1 contains word

addresses 08h to 0Fh. If a page write command

attempts to write across a physical page boundary, the

result is that the data wraps around to the beginning of

the current page (overwriting data previously stored

there), instead of being written to the next page as

might be expected. Therefore, it is necessary for the

application software to prevent page write operations

that would attempt to cross a page boundary.

I2C Serial Data Bus

The DS1388 supports a bidirectional I2C bus and data

transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiv-

ing data is defined as a receiver. The device that con-

trols the message is called a master. The devices that

are controlled by the master are slaves. The bus must

be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions. The DS1388

operates as a slave on the I2C bus. Connections to the

bus are made through the open-drain I/O lines SDA

and SCL. Within the bus specifications, a standard

mode (100kHz maximum clock rate) and a fast mode

(400kHz maximum clock rate) are defined. The DS1388

works in both modes.

The following bus protocol has been defined (Figure 6):

Data transfer can be initiated only when the bus is

not busy.

During data transfer, the data line must remain stable

whenever the clock line is high. Changes in the data

line while the clock line is high will be interpreted as

control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

high.

Start data transfer: A change in the state of the data

line from high to low, while the clock line is high,

defines a START condition.

Stop data transfer: A change in the state of the data

line from low to high, while the clock line is high,

defines a STOP condition.

Data valid: The state of the data line represents valid

data when, after a START condition, the data line is

stable for the duration of the high period of the clock

signal. The data on the line must be changed during

the low period of the clock signal. There is one clock

pulse per bit of data.

250

VCC

VBACKUP

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TCS3

TCS2

TCS1

TCS0

DS1

DS0

ROUT1

ROUT0

TRICKLE-CHARGE REGISTER (00Ah)

1 0F 16 SELECT

NOTE: ONLY 1010b ENABLES CHARGER

1 OF 2

SELECT

1 OF 3

SELECT

TCS0-3 = TRICKLE-CHARGE SELECT

DS0-1 = DIODE SELECT

ROUT0-1 = RESISTOR SELECT

Figure 5. Programmable Trickle Charger

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